The present invention relates to the field of non-volatile semiconductor memory devices, and more particularly, to a synchronous non-volatile memory device having an independent asynchronous boot block.
Non-volatile memory devices include a variety of semiconductor memory devices which have cells that maintain their data when the power is removed from the devices. Types of non-volatile memory devices include flash memories and electrically erasable programmable read only memories (EEPROM), as well as a variety of other device constructions. Typically, these types of memories operate asynchronously or, synchronously with a device system clock, in order to read data from the memory array and to program/write data into the memory array.
Often times, non-volatile devices include a boot block, which is a dedicated area of the memory which is used to store special programs such as an operating system, a BIOS (Basic Input Output System), and the like. Generally, the data in these boot blocks are accessed the same way the rest of memory is accessed. Therefore a synchronous non-volatile device will tend to access data in boot block synchronously with the clock used for the rest of the memory array. The disadvantage to this is that the clock signal and read commands need to be established before the data from the boot block can be accessed. It would be advantageous to be able to access the data from the boot block right away after power up without having to set up the clock or read commands. To do so the boot block would need to operate asynchronously with respect to the regular synchronous main memory portion of the memory device.
U.S. Pat. No. 5,197,034 to Fandrich et al. discloses a non-volatile memory including a main block and a boot block. Circuitry means are coupled to receive a control signal as a control input for allowing the boot block to be updated when the control signal is in a first voltage state and for generating a power off signal to switch the memory into a substantially powered off state when the control signal is in another voltage state.
U.S. Pat. No. 5,402,383 to Akaogi discloses an electrically erasable non-volatile semiconductor memory device for selective use in boot block type or normal type flash memory devices. The device has a memory cell array, a first erase unit, a second erase unit, and an operation establish unit. When a first operation mode is established, the erasing operation of the memory cell array is carried out by a first erase unit only. When a second operation mode is established, the erasing operation of the first erase unit is disabled and the second erase unit is activated to carry out the erase operation. Therefore, the change between the boot block flash memory and a normal-type flash memory can be realized by changing an established value of the operation mode unit.
U.S. Pat. No. 5,502,835 to Le et al. describes a method for synchronously accessing memory in which an integrated circuit microprocessor reads data from an external memory device through early overlapping memory access cycles, thus allowing efficient accesses to slower speed memory. The circuitry includes a boot region that stores the boot routine. The boot region is part of the chip select generation unit shown in FIG. 13 of the Le et al. patent, and appears to be synchronous.
It is an object of the present invention to provide a synchronous non-volatile memory device having a boot block that can be accessed asynchronously and can still be programmed/erased in a synchronous operation.
It is a further object of the present invention to provide a synchronous non-volatile memory device that can either allow the asynchronous boot block to be active after the device is initially powered up or allow switching from synchronous operation to activate the asynchronous boot block upon the assertion of a regular synchronous memory operational command.
The above objects have been achieved by a nonvolatile memory device having a main memory block that operates synchronously with the system clock and an independent asynchronous boot block. This device construction can be used upon initial power up and system reset operations for configuration of the microprocessor/memory controller in which the device is used. The synchronous non-volatile memory device includes control logic circuitry which can allow the asynchronous boot block to be active after initial power up or can allow the boot block to be activated in synchronous mode and then be switched to asynchronous mode. This allows data to be read immediately from the boot block without having to wait for the clock or read command signals to be established.